GDDR6, an abbreviation for graphics double data rate type six synchronous dynamic random-access memory, is a modern type of synchronous graphics random-access memory (SGRAM) with a high bandwidth ("double data rate") interface designed for use in graphics cards, game consoles, and high-performance computation. The finalised specification was published by JEDEC in July 2017. GDDR6 offers increased per-pin bandwidth (up to 16 Gbps) and lower operating voltages (1.35 V), increasing performance and decreasing power consumption relative to GDDR5/GDDR5X.

The Innosilicon GDDR6 PHY is the world’s first silicon proven commercial GDDR6 IP, it is fully compliant to the JEDEC GDDR6 (JESD250) standard, supporting up to 16 Gbps per pin. The GDDR6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits. With Speeds up to 16 Gbps per pin the Innosilicon GDDR6 PHY will offer a maximum bandwidth of up to 64 GB/s. This PHY will be available in advanced FinFET nodes for leading-edge customer integration. The Innosilicon system-aware design methodology used for IP Cores delivers a customer focused experience with improved time-to-market and first-time-right quality. Innosilicon offers flexible delivery of IP cores and will work directly with the customer to provide a full system signal and power integrity analysis, creating an optimized chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.


  • Data rate up to 16Gbps/Pin
  • GDDR6 and GDDR5 Combo
  • Pseudo open drain (POD‐135) compatible outputs
  • Support both Quad data rate (QDR) and double data rate(DDR) data (WCK) mode
  • Driver strength and ODT auto calibration
  • Support both Write and Read CRC
  • Per bit Tx and Rx data phase adjustment
  • Internal high performance low jitter PLL
  • Support both hardware and software training for WCK2CK training, Command training, Read training, Write training
  • Tx de-emphasis EQ and Rx DFE EQ to improve signal integrity
  • Dynamic eye-diagram training for Write and Read operation
  • Internal VREF with DFE for data inputs, with receiver characteris tics programmable per pin
  • Data bus inversion (DBI) and CA bus inversion (CABI)
  • support EDC full rate and half rate hold pattern, programmable EDC tracking bandwidth
  • Various Low power modes


  • World’s first silicon proven commercial GDDR6 IP
  • Advanced process node: GF14nm
  • JEDEC JESD250 standard compliant
  • 2 channels @ 16 bits/channel, Up to 16Gbps/pin, GDDR6 and GDDR5 Combo
  • hardware and software training, Dynamic eye-diagram training
  • Various Low power modes



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