The Innosilicon eDP DP PHY is a highly reliable solution for your display interface requirements. It is fully compliant with DP 1.2 and eDP 1.4 standards, and capable of driving 5.4Gb/s per lane in configurations up to 4 lanes.

Designed with ease of integration in mind, it is configurable via its I2C, APB or CPU interface, and production testing is simplified through at-speed BIST, scan, loopback modes and boundary scan.

The PHY itself is fully self-contained, requiring no end user synthesis, and is optimized for both area and power. It contains all the necessary PHY components such as I/Os, primary and secondary ESD, PLL and the data symbol Synchronization/Serialization unit.

As with all Innosilicon IP, we are ready to provide the custom solution that meets your needs.


  • Silicon proven in GLOBALFOUNDRIES & SMIC
  • Easily ported into any technology
  • Uses standard chip digital and IO supplies
  • Compliant with DP 1.2 and eDP 1.4 standards
  • Drives up to 5.4 Gb/s per lane
  • Available in 1-4 lane PHY configurations
  • Output the link rate clock or half link rate clock, with or without SSC modulation
  • Supports transceiver for AUX channel working in 1MHz Manchester II coding mode
  • Area <0.62mm^2
  • Low pin count
  • 20-bit, 8b/10b data encoding, parallel input bus
  • Built-in low jitter PLL
  • Embedded primary and secondary ESD provides 2000V HBM, 200V MM and 500V CDM
  • The design is latch-up tolerant to 200mA
  • Production test supported with BIST, scan, boundary scan and loop back
  • Deliverables support all major EDA tools


  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include
    • lTest chips and test boards
    • lFPGA integration support
    • lChip level integration



告訴我們您的IP需求 我們將提供定制化方案,滿足您的所有需求!
体育彩票走势图综合版 输入法打字赚钱会泄露隐私吗 内蒙古选五走势图 基本 做房地产销售真能赚钱吗 2019年送彩金网站大全 神雕侠侣手游可以赚钱吗 河南打的是什么麻将 快三押大小稳赚不赔方法独胆 dnf稳赚钱 哪些建筑材料赚钱 贵州快三最新预测 极速快乐十分是真的吗 幸运飞艇助彩计划 七星彩计划软件 云南快乐10分中奖规则 友乐广西麻将安卓版下载 今日贵州快3推荐号码